The present invention relates generally to designing electronic circuits such as integrated circuits, and more particularly to optimizing placement of circuit resources.
Modern integrated circuits often have millions of circuit elements (i.e., resources) such as gates, latches, and drivers in addition to scores of I/O pins. Each of these circuit elements must be placed and electrically connected to other circuit elements, or to I/O pins, via wires (a.k.a. traces). The process of determining the connection path for the circuit wires is referred to as routing.
An initial timing analysis for an un-routed circuit may assume an optimal routing, such as a ‘Steiner’ routing, for each path in the circuit based on using horizontal and vertical routing channels to connect initially placed circuit elements. The initial timing analysis may compute a slack for each path in the circuit that is the difference of a desired arrival time (which may include a timing margin) and the estimated arrival time. A positive slack indicates that the arrival time at a node can be increased without affecting the overall delay of the circuit. Conversely, a negative slack indicates that a signal path is too slow, and the signal path must be sped up.
Optimization of an integrated circuit to meet design specifications often requires speeding up signal paths that have negative slack. In addition to timing improvement, placement related optimizations may be done to improve power, decrease congestion, and decrease consumed area. Typically, performing such optimizations requires resizing and/or moving various circuit elements to achieve the desired objectives. Such optimizations may be conducted during both the placement and routing phases of circuit design. With millions of circuit elements involved, such optimizations can be extremely time consuming.